SiFive Internal Release 1.16.0

What's Changed

• Lower muxes feeding registers to ifs
• Support GrandCentral internalPath on Modules
• Allow GrandCentral source and companion modules to be further apart in the hierarchy
• Improvements to aggregate preservation towards lowering 1-dimensional vector to Verilog
• Add canonicalizer to simplify an array where all elements are identical

New Contributors

• @jackkoenig made their first contribution in #3829

Full Changelog: sifive/1/15/0...sifive/1/16/0