SiFive Internal Release 1.17.0

Overview

• Improvements to HW canonicalizers and ExportVerilog
• New wire spilling heuristics in PrepareForEmission
• RefType and RefOp improvements
• Enhanced SVExtractTestCode to extract some instances and inline modules that just wrap extracted test code
• Performance improvement in verifier

What's Changed

• [FIRRTL][CheckCombCycles] Ignore register self initialization connects by @prithayan in #3965
• Revert "[FIRRTL] Verify FModuleLike's have unique port names." by @dtzSiFive in #3976
• [PrepareForEmission] Fix UAF by @uenoku in #3984
• [FIRRTL] Reuse HierPathOp's when creating in LA, fix GC(T) cleanup, add SymbolDCE to pipeline by @dtzSiFive in #3979
• [SV] Erase empty if-else block by @uenoku in #3988
• [FIRRTL][LowerTypes] Lower aggregate type operand by @prithayan in #3982
• [PrepareForEmission] Perform wire spilling based estimated expression size by @uenoku in #3752
• [FIRRTL][RefType] Add a new RefSub Op by @prithayan in #3993
• [FIRRTL][LowerXMR] Lower RefSubOp to memory XMR by @prithayan in #3994
• [ExportVerilog] Improve XMR emission when used as bound inputs by @uenoku in #3995
• [FIRRTL][RefType] Lower RefType in LowerTypes by @prithayan in #3990
• [HW] Enable i0 for HWIntegerType by @mortbopet in #3985
• [FIRRTL][LowerAnnotation] Mark the DataTap sink as NoDedup by @prithayan in #4005
• [FIRRTL][GrandCentral] Update attribute wireName to sink by @prithayan in #4006
• [HW] Add hw.struct_explode canonicalizer by @mortbopet in #4010
• [HW] Add PruneZeroValuedLogic to PrepareForEmission by @mortbopet in #3935
• [FIRRTL] Fix GCT Instance Name Prefix by @seldridge in #4016
• [FIRRTL][GrandCentral] Revert MemTap sink to array attribute by @prithayan in #4022
• [FIRRTL] Allow foreign types in module/instance ports by @fabianschuiki in #2694
• [ExportVerilog] emit comments on else and endif for readability by @dtzSiFive in #4024
• [SV] Update ExtractTestCode to extract input only modules. by @mikeurbach in #4014
• [FIRRTL][InferWidths] Exclude foreign types, add conversion cast support by @fabianschuiki in #4026
• [FIRRTL][LowerTypes] Pass through foreign types in lowerProducer by @fabianschuiki in #4027
• [FIRRTL][InferResets] Don't abort on foreign types by @fabianschuiki in #4025
• [ExportVerilog] Improve error message for emitting unsupported ops by @mortbopet in #4011
• [HW] Improve asm result names for struct extract, explode ops by @mortbopet in #3998
• [ExportVerilog] Handle hw.struct_explode by @mortbopet in #4012
• [PrepareForEmission] Improve namehints heuristic and add mux heuristic by @uenoku in #4019
• [PrettifyVerilog] Fix a crash caused by comparing different width of APInt by @uenoku in #4031
• [ExportVerilog][NFC] Remove blockDeclaration* tracking as unused. by @dtzSiFive in #4046
• [ExportVerilog][NFC] Drop another unused tracking cursor. by @dtzSiFive in #4049
• [HW] Add a folder for array slice op by @uenoku in #4052
• Don't read lowering options from hidden global options by @darthscsi in #4038
• [SV] Allow packed arrays for index part select inout by @uenoku in #4051
• [FIRParser] Stop double deserializing OMIR annos by @youngar in #4062
• [FIRRTL][Dedup] Update few error messages by @prithayan in #4037
• [ExportVerilog] Fix use of wrong decl alignment after emitting a block. by @dtzSiFive in #4054
• [FIRRTL] Implement out-of-bounds as array extension by @darthscsi in #4069
• [HW] Add a folder for a constant array created by a bitcast by @uenoku in #4066
• [ExtractTestCode] Support extracting instances in some cases. by @mikeurbach in #3522
• [NFC] Cache sybmol lookup removing O(N^2) behavior from CircuitOp::verify by @darthscsi in #4077
• [SV] Update ExtractTestCode to inline input only modules. by @mikeurbach in #4063
• [Seq] Add FirReg no-update canonicalizer by @youngar in #4060
• [SV] Fix heap-use-after-free in recent SVExtractTestCode change. by @mikeurbach

Full Changelog: sifive/1/16/0...sifive/1/17/0