SiFive Internal Release 1.17.0

Overview

• Improvements to HW canonicalizers and ExportVerilog
• New wire spilling heuristics in PrepareForEmission
• RefType and RefOp improvements
• Enhanced SVExtractTestCode to extract some instances and inline modules that just wrap extracted test code
• Performance improvement in verifier

What's Changed

• [FIRRTL][CheckCombCycles] Ignore register self initialization connects by @prithayan in #3965
• Revert "[FIRRTL] Verify FModuleLike's have unique port names." by @dtzSiFive in #3976
• [PrepareForEmission] Fix UAF by @uenoku in #3984
• [FIRRTL] Reuse HierPathOp's when creating in LA, fix GC(T) cleanup, add SymbolDCE to pipeline by @dtzSiFive in #3979
• [SV] Erase empty if-else block by @uenoku in #3988
• [FIRRTL][LowerTypes] Lower aggregate type operand by @prithayan in #3982
• [PrepareForEmission] Perform wire spilling based estimated expression size by @uenoku in #3752
• [FIRRTL][RefType] Add a new RefSub Op by @prithayan in #3993
• [FIRRTL][LowerXMR] Lower RefSubOp to memory XMR by @prithayan in #3994
• [ExportVerilog] Improve XMR emission when used as bound inputs by @uenoku in #3995
• [FIRRTL][RefType] Lower RefType in LowerTypes by @prithayan in #3990
• [HW] Enable i0 for HWIntegerType by @mortbopet in #3985
• [FIRRTL][LowerAnnotation] Mark the DataTap sink as NoDedup by @prithayan in #4005
• [FIRRTL][GrandCentral] Update attribute wireName to sink by @prithayan in #4006
• [HW] Add hw.struct_explode canonicalizer by @mortbopet in #4010
• [HW] Add PruneZeroValuedLogic to PrepareForEmission by @mortbopet in #3935
• [FIRRTL] Fix GCT Instance Name Prefix by @seldridge in #4016
• [FIRRTL][GrandCentral] Revert MemTap sink to array attribute by @prithayan in #4022
• [FIRRTL] Allow foreign types in module/instance ports by @fabianschuiki in #2694
• [ExportVerilog] emit comments on else and endif for readability by @dtzSiFive in #4024
• [SV] Update ExtractTestCode to extract input only modules. by @mikeurbach in #4014
• [FIRRTL][InferWidths] Exclude foreign types, add conversion cast support by @fabianschuiki in #4026
• [FIRRTL][LowerTypes] Pass through foreign types in lowerProducer by @fabianschuiki in #4027
• [FIRRTL][InferResets] Don't abort on foreign types by @fabianschuiki in #4025
• [ExportVerilog] Improve error message for emitting unsupported ops by @mortbopet in #4011
• [HW] Improve asm result names for struct extract, explode ops by @mortbopet in #3998
• [ExportVerilog] Handle hw.struct_explode by @mortbopet in #4012
• [PrepareForEmission] Improve namehints heuristic and add mux heuristic by @uenoku in #4019
• [PrettifyVerilog] Fix a crash caused by comparing different width of APInt by @uenoku in #4031
• [ExportVerilog][NFC] Remove blockDeclaration* tracking as unused. by @dtzSiFive in #4046
• [ExportVerilog][NFC] Drop another unused tracking cursor. by @dtzSiFive in #4049
• [HW] Add a folder for array slice op by @uenoku in #4052
• Don't read lowering options from hidden global options by @darthscsi in #4038
• [SV] Allow packed arrays for index part select inout by @uenoku in #4051
• [FIRParser] Stop double deserializing OMIR annos by @youngar in #4062
• [FIRRTL][Dedup] Update few error messages by @prithayan in #4037
• [ExportVerilog] Fix use of wrong decl alignment after emitting a block. by @dtzSiFive in #4054
• [FIRRTL] Implement out-of-bounds as array extension by @darthscsi in #4069
• [HW] Add a folder for a constant array created by a bitcast by @uenoku in #4066
• [ExtractTestCode] Support extracting instances in some cases. by @mikeurbach in #3522
• [NFC] Cache sybmol lookup removing O(N^2) behavior from CircuitOp::verify by @darthscsi in #4077
• [SV] Update ExtractTestCode to inline input only modules. by @mikeurbach in #4063
• [Seq] Add FirReg no-update canonicalizer by @youngar in #4060
• [SV] Fix heap-use-after-free in recent SVExtractTestCode change. by @mikeurbach

Full Changelog: sifive/1/16/0...sifive/1/17/0

SiFive Internal Release 1.16.0

What's Changed

• Lower muxes feeding registers to ifs
• Support GrandCentral internalPath on Modules
• Allow GrandCentral source and companion modules to be further apart in the hierarchy
• Improvements to aggregate preservation towards lowering 1-dimensional vector to Verilog
• Add canonicalizer to simplify an array where all elements are identical

New Contributors

• @jackkoenig made their first contribution in #3829

Full Changelog: sifive/1/15/0...sifive/1/16/0

SiFive Internal Release 1.5.3

What's Changed

• Backport: [FIRRTL][SV] Add comment attribute to GC interfaces and modules by @youngar in #3923

Full Changelog: sifive/1/5/2...sifive/1/5/3

SiFive Internal Release 1.15.0

What's Changed

• Fix crash with memories with 0-width data
• Split large variadic operations into expressions, improving VCS compile time
• Hide some developer oriented command line options
• Allow DFT "test_en" signal to be located outside of the DUT
• Improved code generation for the random initialization of registers

Full Changelog: sifive/1/14/0...sifive/1/15/0

SiFive Internal Release 1.5.2

What's Changed

• [FIRRTL] Backport IMDCE updates to sifive 1.5 by @uenoku in #3771

Full Changelog: sifive/1/5/1...sifive/1/5/2

SiFive Internal Release 1.14.0

Summary of Changes

• Don't use localparam for emitting temporary constants in ExportVerilog
• Restore previous behavior w.r.t. self-assigned registers in PrettifyVerilog
• More RefOp and RefType improvements
• Internal improvements to different caches maintained by the compiler

What's Changed

• [FIRRTL][RefOps] Remove downward-only constraint from RefType by @prithayan in #3753
• [docs] Add text describing the inner symbol classes/traits/verif. by @dtzSiFive in #3743
• [FIRParser] Remove more old annotation handling code by @youngar in #3749
• [FIRRTL][InferRW] Set RWmode to the complement term in Write enable by @prithayan in #3759
• [PrepareForEmission] Don't create localparam as a temporary wire by @uenoku in #3770
• [FIRRTL][RefOps] LowerXMR: Handle upward references by @prithayan in #3745
• [FIRRTL] Keep InstancePathCache updated by @prithayan in #3773
• [FIRRTL] Keep the Annotation Target Caches updated by @prithayan in #3772
• [PrettifyVerilog] No longer remove self-assignments to whole names by @nandor in #3763

Full Changelog: sifive/1/13/0...sifive/1/14/0

SiFive Internal Release 1.13.0

Overview of Changes

• Retain stable register randomization initialization through transformation
• Apply stable register randomization to all modules by breaking up large initial registers into smaller ones
• More RefType operations work for XMRs
• New SystemC functionalities

What's Changed

• [FIRRTL][RefOps] NoSideEffects, InferTypeOpInterface, asm result names by @dtzSiFive in #3727
• [FIRRTL] Lower RefType Operations to XMR by @prithayan in #3719
• [FIRRTL][LowerXMR] Handle xmr to ports correctly by @prithayan in #3730
• [FIRRTL][IMDCE] Test deleting code w/ref's. Avoid temp ref wire. by @dtzSiFive in #3716
• [ExportSystemC] Basic infrastructure for emission by @maerhart in #3726
• [FIRRTL][InferResets] Handle RefType, send, resolve. by @dtzSiFive in #3729
• [FIRRTL] Fix use of attribute from erased op. by @dtzSiFive in #3746
• [FIRRTL][Utils] Add getBaseType, mapBaseType helpers. by @dtzSiFive in #3744
• [FIRRTL] Extend register randomization to split up large registers. by @mikeurbach in #3748
• [ExportSystemC] Integer and port type emission by @maerhart in #3733
• [SystemC] Don't hardcode includes by @maerhart in #3734
• [ExportSystemC] Add emission patterns for the remaining systemc ops and constant op by @maerhart in #3735

Full Changelog: sifive/1/12/0...sifive/1/13/0

SiFive Internal Release 1.12.0

Overview of Changes

• Verilog emission refactoring and simplification (no major change to Verilog output)
• Bugfixes in annotation handling and Verilog emission
• Simplify printing of dedupe failure of instances
• Refactoring to make registers more amenable to analysis and transformation (no major change to Verilog output)
• Early work to support new reference types and operations
• Support optional version specifier in .fir files
• Register randomization stability improvement between release and debug modes of firtool

What's Changed

• Convert firrtl IsX assert forms to real ops by @darthscsi in #3642
• [PrepareForEmission] Don't spill wires in procedural regions by @uenoku in #3551
• [SV][Seq][FIRRTL] Lowered FIRRTL registers to seq.firreg by @nandor in #3191
• [FIRRTL] Use annotations to represent dontTouch by @uenoku in #3639
• [HW] Added simple canonicalizers to hw.struct_inject and hw.struct_extract by @nandor in #3644
• [ExportVerilog] Directly emit declarations when spillWiresAtPrepare by @uenoku in #3597
• [Docs][Seq] Documented seq.firreg in the seq documentation by @nandor in #2945
• [HW][FIRRTL] Fix InnerRefAttr's subelement walk/replace. by @dtzSiFive in #3645
• [ExportVerilog] Fix wire name collision by @uenoku in #3661
• [FIRRTL] Update port symbols to InnerSymAttr by @prithayan in #3582
• [HW] Added verifier for hw.struct_create by @nandor in #3674
• [FIRRTL] Allow annotations to be placed on PrintF ops by @nandor in #3676
• [ExportVerilog] Inline array element accesses by @nandor in #3675
• [HW] Added canonicalizers for aggregate operations by @nandor in #3671
• [FIRRTL][SFCCompat] Add support for aggregates by @youngar in #3670
• [FIRRTL] Organize all existing types under FIRRTLBaseType. by @dtzSiFive in #3666
• [IMDCE] Forward constant output ports to caller sides by @uenoku in #3688
• [FIRRTL][Dedup] Simplify printing of dedup failure of instances by @youngar in #3689
• [FIRRTL] Add RefType, first non-base type. by @dtzSiFive in #3653
• [ExportVerilog] Fix incorrect inlining of automatic logic by @uenoku in #3691
• [ExportVerilog] Inline logic assignments into decl in new emission mode by @uenoku in #3692
• [FIRRTL] Support optional version in fir files by @darthscsi in #3709
• [FIRRTL] Add the FIRRTL RefType Ops by @prithayan in #3700
• [FIRRTL] Move RefOps to Expressions instead of Statements. NFC by @prithayan in #3710
• [ExportVerilog] Enable new emission mode by default by @uenoku in #3695
• [FIRRTL] Ignore InstanceOp in field sensitive symbol verifier by @prithayan in #3723
• [FIRRTL][IMCP] Add support for ref send/resolve. by @dtzSiFive in #3711
• [FIRRTL] Set the parameters for register randomization early. by @mikeurbach in #3714

New Contributors

• @bluewww made their first contribution in #3638
• @alandy made their first contribution in #3718

Full Changelog: sifive/1/11/0...sifive/1/12/0

SiFive Internal Release 1.11.0

What's Changed

• Smaller installed binary sizes
• Fixed bug in LowerToHW when sinks are used as sources
• Stop removing registers with annotations during canonicalization
• Better simplification of attach operations
• Fix bug in module inlining with non-local annotations

New Contributors

• @andrewb1999 made their first contribution in #3580
• @TaoBi22 made their first contribution in #3599
• @zyedidia made their first contribution in #3617

Full Changelog: sifive/1/10/0...sifive/1/11/0

SiFive Internal Release 1.10.0

What's Changed

• Add stats to various memory-related passses
• Fix python binding installation
• Lowered struct inject/array concat to sv.passign of individual fields/elements
• Handle more annotations: DecodeTableAnno, BlackBoxTargetDirAnno,
• Ignore memory with zero bit data
• Add optimization option -O [debug|release]

Full Changelog: sifive/1/9/0...sifive/1/10/0